Structured Hardware Compilation of Parallel Programs
نویسندگان
چکیده
A major bottleneck in automatic hardware synthesis is the time to place and route the netlist produced by a hardware compiler. This paper presents a method which exploits the syntax of the source program to guide its layout in a deviceindependent manner. The technique has been used in prototyping a hardware compiler for a commercially-available device, the Algotronix CAL1024 FieldProgrammable Gate Array. The potential of this approach is evaluated.
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